Embedded memories have been a vital component of system-on-chip solutions for decades. However, memory blocks occupy a significant portion of the chip's die area, making it an important component in terms of area and power consumption. With increasing demand for battery-operated applications, methods for reducing power consumption of the memory blocks have received significant interest. In particular, static random access memory (SRAM) has been receiving a lot of attention.
Six-transistor SRAM cells are preferred for many applications because of their high speed and small area. This configuration, however, suffers from high stand-by power consumption due to leakage. Additionally, the power consumption of the write operation is high because of a high swing of the bit-line voltages. Specifically, for a write operation, the swing of the bit-line voltage should be high enough to overwrite the cell's data. Such a swing makes the write operation a power consuming operation. To overcome these problems, several methods have been proposed.
One approach, as described by H. Mizuno and T. Nagano in “Driving source-line cell architecture for sub-1-v highspeed low-power applications,” IEEE J. Solid-State Circuits, vol. 31, pp. 552-557, 1996 teaches a virtual grounding scheme. As taught by Mizuno, the source of the drive transistors is connected to a virtual ground instead of to VSS. The drive capability of the drive transistors and the leakage current of the cell can be controlled by controlling the virtual ground voltage. For a data retention mode, the virtual ground is kept close to the supply voltage VDD to reduce the leakage current. This modification makes the voltage high and voltage low of the cell close to each other. For a read operation, the virtual ground decreases substantially. This operation boosts the strength of the drive transistors that need to discharge a bit-line voltage. For a write operation, the virtual ground goes to a high impendence mode and destroys the data of the cell. This operation charges up all node voltages of the cell to the supply voltage VDD, leaving the transistors in a weak cut-off operating region. Under this condition, a low voltage swing on the bit-line can produce sufficient charge within the cell nodes to write the data onto the cell. The virtual ground of a group of transistors can be connected to share the control circuitry for that node.
As described by N. Shibata in “A switched virtual-gnd level technique for fast and low power srams,” IEICE Trans. Electron., vol. E80-C, pp. 1598-1607, 1997, a method for using the virtual grounding scheme to reduce the leakage current and bit-line voltage swing is proposed. As taught by Shibata, a virtual ground is shared among the cells in the same column and controlled using a column decoder. When the cells of a specific column are in the data retention mode, the virtual ground of that column is close to the supply voltage. When a cell is a target of the read operation, the virtual ground of the whole column is lowered to the actual ground VSS to increase the drive of the cell. However, since the virtual ground is connected to all cells in the column, it is highly capacitive. Accordingly, fluctuating the voltage of the virtual ground node is power consuming. Thus, the read operation of this scheme is a high-power consuming operation.
As described by K. Kanda, S. Hattori, and T. Sakurai, in “90% write power-saving SRAM using sense-amplifying memory cell,” IEEE J. Solid-State Circuits, vol. 93, pp. 929-933, 2004, an alternative virtual grounding scheme is proposed. As taught by Sakurai, the virtual grounds of the cells on the same row are connected and controlled using a row decoder. The virtual ground provides sufficient voltage swing for the cell to retain data in the data retention mode while keeping the transistors in a low-leakage operating region. In write operations, the swing of the bit-lines is reduced at the expense of destroying data of the cells in the same row. Therefore, this scheme is not useful in practical cases in which we are interested in having multiple words in the same row. Further, since the virtual ground is connected to all cells in the row, it is highly capacitive. Accordingly, fluctuating the voltage of the virtual ground for both read and write operations consumes significant power.
Thus it can be seen that there is a need for a virtual grounding scheme that overcomes at least some of the problems of the prior art.